The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. In particular, the invention provides a method and system for monitoring and controlling process related information for the manufacture of semiconductor integrated circuit devices. More particularly, the invention provides a method and system using a reverse arrangement process for a trend test(s) for statistical process control used in the manufacture of semiconductor integrated circuit devices. But it would be recognized that the invention has a much broader range of applicability.
Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Conventional integrated circuits provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits.
Increasing circuit density has not only improved the complexity and performance of integrated circuits but has also provided lower cost parts to the consumer. An integrated circuit or chip fabrication facility can cost hundreds of millions, or even billions, of U.S. dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of integrated circuits on it. Therefore, by making the individual devices of an integrated circuit smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in integrated fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. Additionally, as devices require faster and faster designs, process limitations exist with certain conventional processes, including monitoring techniques, materials, and even testing techniques.
An example of such processes include ways of monitoring process related functions during the manufacture of integrated circuits, commonly called semiconductor devices. Such monitoring process is often desired for continuously improving quality and productivity to stay competitive. As merely an example, statistical process control (SPC) has been playing an important role in conventional industries. It is a procedure in which data are collected, organized, analyzed and interpreted. Actions are requested to identify root causes and to implement solutions so a process can be maintained at its desired level or be improved to a higher level. SPC makes use of statistical signals to identify sources of variation, to correct identified variation causes therefore to improve performance, and to maintain control of processes. Variations are classified as common (random or chance) and special (or assignable) causes in general [1]. Common causes denote the many sources of variation within a process that is in statistical control. Special causes refer to any factors causing variation that cannot be adequately explained by a single distribution. A process in statistical control operates with less variability than a process having special causes. Unless all the special causes of variance are identified and corrected, they will continue to affect the process outputs in unpredictable and undesirable ways.
Control charts (which are trend charts with control limits) are often used to monitor selected parameters, which have important quality characteristics. Various run tests have been developed to identify if there is any pattern in the data points. Western Electric developed five run tests [2]; they are 1) 1 point beyond 3 sigma, 2) 2 out 3 successive points beyond 2 sigma, 3) 4 out of 5 successive points beyond 1 sigma, 4) 15 successive points not within 1 sigma of center line, and 5) 8 successive points on the same side and not within 1 sigma of center line. Later in about 1986, Nelson developed additional 3 rules [3]: 1) 9 successive points on same side of center line, 2) 6 successive points steadily increasing or decreasing, and 3) 14 successive points alternating up and down.
The run test of 6 consecutive points increasing or decreasing, proposed by Nelson is a special test of the trend pattern, indicating an instable process. It is usually assumed that the change will be monotonic and is either increasing or decreasing over time. The ease of such monotonic trend test becomes popular due to the practical values. However, this test obviously cannot detect all possible trends and we should be aware that the change may be non-monotonic (i.e., fluctuating). Other limitations also exist with these conventional techniques. These and other limitations are described throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for manufacturing semiconductor devices is desired.